Semiconductor memory devices include a memory cell array wherein data is stored in memory cells in the memory cell array. Conventionally, after memory cells are erased, an erase verify operation is performed to verify that the memory cell is fully erased. Erase verify is typically performed by comparing a current across a memory cell to a constant reference current. As memory cells are programmed and erased (generally referred to as cycling), their electrical characteristics degrade, resulting in reduced cell current at a given voltage. Effectively, the cycled memory cells are overerased. Currents at voltages below the memory cell threshold voltage are significantly increased in cycled cells due to cycling degradation of the memory cell and overerase thereof. The increased subthreshold current increases bitline-to-bitline current leakage under unselected word lines when a selected memory cell is programmed or soft-programmed. The increased bitline-to-bitline current leakage increases total programming current, thereby increasing power consumption during programming. In addition, the drain voltage on the bitline must necessarily be increased to overcome the voltage drop due to the bitline-to-bitline leakage, thereby negatively impacting the operation of the DC-DC charge pumps.
Accordingly, it is desirable to provide a method and apparatus for adaptively compensating for memory cell degradation due to overerase in semiconductor memory devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.